1. Field of the Invention
The present invention relates to high frequency semiconductor devices, and in particular, to a multilayer wiring structure for monolithic microwave integrated circuit (MMIC) for use in the gigahertz or higher frequency spectrum.
2. Description of the Related Art
In an MMIC in which high speed semiconductors such as high-electron-mobility transistors (HEMTs) and hetero-bipolar transistors (HBTs) are integrated with passive devices such as capacitors and resistors, microstrip transmission lines which have superior signal transmission characteristics in high frequency region are generally used for transmitting signals among devices. For increasing the integration density of the MMIC, the transmission lines are normally multilayered.
FIGS. 1A and 1B show the structure of an MMIC according to the related art. FIG. 1A shows a plan view of the MMIC, and FIG. 1B shows a cross-sectional view taken along the line IB—IB in FIG. 1A. As shown in FIG. 1B, an active device 2 such as an HEMT and a passive device 3 such as a capacitor or a resistor are formed on a surface of a gallium arsenide (GaAs) substrate 1. The devices 2 and 3 are covered with a surface insulating layer 4, and a ground plate 5 is formed thereon which has a potential fixed to the ground potential. Insulating interlayers and wiring layers are alternately stacked on the ground plate 5, in accordance with the required level number of wiring layers.
Specifically, FIG. 1B shows a three-layer wiring structure in which wiring layers 51, 53, and 55 are alternatively stacked, with insulating interlayers 50, 52, and 54 provided therebetween. Each of the wiring layers 51, 53, and 55 combines with the ground plate 5 to form a transmission line. The connection between two wiring layers and the connection between each wiring layer and each device are established by through-holes (not shown), as required.
In the MMIC having the above multilayered structure, two wiring layers may cross each other as a result of circuit arrangement. As shown in FIGS. 1A and 1B, the wiring layer 51 as a first level crosses the wiring layer 53 as a second level, with the insulating interlayer 52 provided therebetween. The wiring layer 51 as the first level also crosses the wiring layers 55 as a third level, with the insulating interlayers 52 and 54 provided therebetween.
When two wiring layers cross each other, as described above, the transmission characteristics deteriorate, for example, signal leakage may occur, because signals transmitted by transmission lines made of wiring layers mutually interfere where they cross one another. To prevent the deterioration, a method is employed in which, by forming an insulating interlayer between upper and lower wiring layers which cross each other, and providing a separation plate on the insulating interlayer, the wiring layers are electrically separated.
FIG. 2 shows a cross-sectional view of an improved multilayered wiring structure for MMICs. This structure has an additional insulating interlayer 56 inserted among wiring layers 51 and 53 which cross each other. The insulating interlayer 56 has a separation plate 57 provided on the entirety thereof. The wiring layer 51 as a first level combines with a ground plate 5 to form a microstrip transmission line. Similarly, both the wiring layer 53 as a second level and the wiring layers 55 as a third level combine with the separation plate 57 to form transmission lines. This arrangement electrically separates crossing transmission lines made of the wiring layers 51, 53, and 55.
Although the multilayered wiring structure shown in FIG. 2 is effective in preventing interference among transmission lines where they cross each other, the insulating interlayer 56 for providing the separation plate 57 must be inserted. This causes a problem in that the number of insulating interlayers increases, thus increasing the thickness of the overall multilayered wiring structure.
The connection between two wiring layers and the connection between each wiring layer and each semiconductor device are established by throughholes in accordance with the circuit design requirements. When the top wiring layer is connected to the semiconductor device, throughholes which penetrate all stacked insulating interlayers must be formed. However, as described above, when the total thickness of the multilayered wiring structure is increased due to the increased number of insulating interlayers, it is difficult for the production process to form minute throughholes.
Accordingly, when the increase in the total thickness is reduced by reducing the thicknesses of the insulating interlayers, the characteristic impedance of the transmission lines which have the insulating interlayers therebetween decrease, resulting in deterioration in the transmission characteristics. To avoid this problem, if the transmission characteristics of the transmission lines is maintained at a predetermined value, the width of each wiring layer must be reduced, resulting in the problem of the increased transmission loss.